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A class of power-efficient VLSI architectures for high-speed turbo-decoding

dc.contributor.authorBougard, Bruno
dc.contributor.authorGiulietti, Alexandre
dc.contributor.authorVan der Perre, Liesbet
dc.contributor.authorCatthoor, Francky
dc.date.accessioned2021-10-14T21:11:14Z
dc.date.available2021-10-14T21:11:14Z
dc.date.issued2002
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/6060
dc.sourceIIOimport
dc.titleA class of power-efficient VLSI architectures for high-speed turbo-decoding
dc.typeProceedings paper
dc.contributor.imecauthorCatthoor, Francky
dc.contributor.orcidimecCatthoor, Francky::0000-0002-3599-8515
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage549
dc.source.endpage553
dc.source.conferenceProceedings IEEE Global Telecommunications Conference - Globecom
dc.source.conferencedate17/11/2002
dc.source.conferencelocationTaiwan R.O.C.
imec.availabilityPublished - open access
imec.internalnotesVol. 1


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