An FPGA-Based Programmable ALPG Platform With Hardware Loop Profiling and a Fully Custom PHY for DRAM Fault Diagnosis

Abstract

The increasing fault rate in DRAM due to aging and advanced nanoscale fabrication exposes critical limitations of traditional testing methods, including Automatic Test Equipment (ATE) and Memory Built-In Self-Test (MBIST). These conventional approaches rely on fixed test patterns and static timing configurations, rendering them ill-equipped to detect timing-sensitive failures such as Write Recovery Errors (WREs) and Variable Retention Time (VRT) faults that emerge throughout a memory’s operational lifetime. This paper presents a flexible, FPGA-based Algorithmic Pattern Generator (ALPG) platform designed for programmable and cost-effective DRAM fault diagnosis that complements, rather than replaces, ATE for post-manufacturing testing. Building on prior open-source FPGA-based DRAM testing infrastructures that already provide programmable command interfaces and runtime timing control, the platform integrates a custom 32-bit ALPG Instruction Set Architecture (ISA) supporting 17 distinct test patterns that cover 11 fault types, and a custom PHY built directly from FPGA I/O primitives—without modifying any vendor PHY IP—that enables runtime adjustment of JEDEC timing parameters. The principal novel contributions are: (i) a hardware Loop Profiler with three-iteration, basic-block-level loop detection that reduces instruction cycle overhead for loop-intensive test sequences; (ii) the formalization of a Pattern and Timing Space Coverage (PTSC) metric; and (iii) the integration of these into a compact, ASIC-synthesizable ALPG diagnosis engine. Synthesized on a Samsung 28 nm library, the ASIC-synthesizable ALPG core (excluding the FPGA-based custom PHY) maintains a compact gate count of 26.2K, and the PTSC metric—a structural measure of the testable pattern-and-timing space—shows a 3.4× improvement over existing ALPG frameworks and is shown to be robust to the normalization choice. The current implementation targets DDR4; extension to LPDDR5 and DDR5, together with empirical in-field, aging, and VRT characterization, is identified as future work. Show Less