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System-level performance optimization of the diata queueing memory management in high-speed network processors

dc.contributor.authorCouvreur, Chantal
dc.contributor.authorNikologiannis, A.
dc.contributor.authorKonstantoulakis, G.
dc.contributor.authorLambrecht, Jürgen
dc.contributor.authorVerkest, Diederik
dc.contributor.authorCatthoor, Francky
dc.date.accessioned2021-10-14T21:17:39Z
dc.date.available2021-10-14T21:17:39Z
dc.date.issued2002
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/6149
dc.sourceIIOimport
dc.titleSystem-level performance optimization of the diata queueing memory management in high-speed network processors
dc.typeProceedings paper
dc.contributor.imecauthorVerkest, Diederik
dc.contributor.imecauthorCatthoor, Francky
dc.contributor.orcidimecVerkest, Diederik::0000-0001-6567-2746
dc.contributor.orcidimecCatthoor, Francky::0000-0002-3599-8515
dc.source.peerreviewno
dc.source.beginpage518
dc.source.endpage523
dc.source.conferenceProceedings 39th Design Automation Conference
dc.source.conferencedate10/06/2002
dc.source.conferencelocationNew Orleans, LA USA
imec.availabilityPublished - imec


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