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In-line electrical metrology for high-k gate dielectrics deposited by atomic layer chemical vapour deposition

dc.contributor.authorDe Witte, Hilde
dc.contributor.authorMaes, Jan
dc.contributor.authorPassefort, S.
dc.contributor.authorBesling, W.
dc.contributor.authorEason, K.
dc.contributor.authorYoung, E.
dc.contributor.authorRittersma, Chris
dc.contributor.authorHeyns, Marc
dc.date.accessioned2021-10-14T21:25:31Z
dc.date.available2021-10-14T21:25:31Z
dc.date.issued2002-09
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/6227
dc.sourceIIOimport
dc.titleIn-line electrical metrology for high-k gate dielectrics deposited by atomic layer chemical vapour deposition
dc.typeJournal article
dc.contributor.imecauthorMaes, Jan
dc.contributor.imecauthorHeyns, Marc
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage111
dc.source.endpage115
dc.source.journalSemiconductor Fabtech
dc.source.issue17
imec.availabilityPublished - open access


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