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A low energy clustered instruction memory hierarchy for long instruction word processors

dc.contributor.authorJayapala, Murali
dc.contributor.authorBarat, Francisco
dc.contributor.authorOp de Beeck, P.
dc.contributor.authorCatthoor, Francky
dc.contributor.authorDeconinck, G.
dc.contributor.authorCorporaal, Henk
dc.date.accessioned2021-10-14T21:54:32Z
dc.date.available2021-10-14T21:54:32Z
dc.date.issued2002
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/6434
dc.sourceIIOimport
dc.titleA low energy clustered instruction memory hierarchy for long instruction word processors
dc.typeProceedings paper
dc.contributor.imecauthorJayapala, Murali
dc.contributor.imecauthorCatthoor, Francky
dc.contributor.orcidimecJayapala, Murali::0000-0001-7917-0149
dc.contributor.orcidimecCatthoor, Francky::0000-0002-3599-8515
dc.source.peerreviewno
dc.source.beginpage258
dc.source.endpage267
dc.source.conferenceIntegrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. 12th International Workshop, PATMOS
dc.source.conferencedate11/09/2002
dc.source.conferencelocationSevilla Spain
imec.availabilityPublished - imec
imec.internalnotesLecture Notes in Computer Science; Vol. 2451


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