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Analysis and modeling of a digital CMOS circuit operation and reliability after gate oxide breakdown: a case study

dc.contributor.authorKaczer, Ben
dc.contributor.authorDegraeve, Robin
dc.contributor.authorRasras, Mahmoud
dc.contributor.authorDe Keersgieter, An
dc.contributor.authorVan de Mieroop, Koen
dc.contributor.authorGroeseneken, Guido
dc.date.accessioned2021-10-14T21:58:59Z
dc.date.available2021-10-14T21:58:59Z
dc.date.issued2002
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/6461
dc.sourceIIOimport
dc.titleAnalysis and modeling of a digital CMOS circuit operation and reliability after gate oxide breakdown: a case study
dc.typeJournal article
dc.contributor.imecauthorKaczer, Ben
dc.contributor.imecauthorDegraeve, Robin
dc.contributor.imecauthorDe Keersgieter, An
dc.contributor.imecauthorGroeseneken, Guido
dc.contributor.orcidimecKaczer, Ben::0000-0002-1484-4007
dc.contributor.orcidimecDe Keersgieter, An::0000-0002-5527-8582
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage555
dc.source.endpage564
dc.source.journalMicroelectronics Reliability
dc.source.issue4_5
dc.source.volume42
imec.availabilityPublished - open access


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