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CMOS scaling to 25nm gate lengths

dc.contributor.authorKubicek, Stefan
dc.contributor.authorDe Meyer, Kristin
dc.date.accessioned2021-10-14T22:05:30Z
dc.date.available2021-10-14T22:05:30Z
dc.date.issued2002
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/6499
dc.sourceIIOimport
dc.titleCMOS scaling to 25nm gate lengths
dc.typeProceedings paper
dc.contributor.imecauthorKubicek, Stefan
dc.contributor.imecauthorDe Meyer, Kristin
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage259
dc.source.endpage270
dc.source.conferenceProceedings of the 4th International Conference on Advanced Semiconductor Devices and Microsystems - ASDAM
dc.source.conferencedate14/10/2002
dc.source.conferencelocationSmolenice Castle Slovakia
imec.availabilityPublished - open access


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