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Optimizing p-type ultra-shallow junctions for the 65 nm CMOS technology node

dc.contributor.authorPawlak, Bartek
dc.contributor.authorLindsay, Richard
dc.contributor.authorSurdeanu, Radu
dc.contributor.authorStolk, Peter
dc.contributor.authorMaex, Karen
dc.date.accessioned2021-10-14T22:44:18Z
dc.date.available2021-10-14T22:44:18Z
dc.date.issued2002
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/6704
dc.sourceIIOimport
dc.titleOptimizing p-type ultra-shallow junctions for the 65 nm CMOS technology node
dc.typeProceedings paper
dc.contributor.imecauthorPawlak, Bartek
dc.contributor.imecauthorMaex, Karen
dc.source.peerreviewno
dc.source.beginpage21
dc.source.endpage14
dc.source.conferenceProceedings of the 14th International Conference on Ion Implantation Technology
dc.source.conferencedate22/09/2002
dc.source.conferencelocationTaos, NM USA
imec.availabilityPublished - imec


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