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Cu interconnects and low-k dielectrics, Challenges for chip interconnections and packaging

dc.contributor.authorBeyne, Eric
dc.date.accessioned2021-10-15T04:01:04Z
dc.date.available2021-10-15T04:01:04Z
dc.date.issued2003
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/7204
dc.sourceIIOimport
dc.titleCu interconnects and low-k dielectrics, Challenges for chip interconnections and packaging
dc.typeProceedings paper
dc.contributor.imecauthorBeyne, Eric
dc.contributor.orcidimecBeyne, Eric::0000-0002-3096-050X
dc.source.peerreviewno
dc.source.beginpage221
dc.source.endpage223
dc.source.conferenceProceedings of the IEEE Interconnect Technology Conference - IITC
dc.source.conferencedate2/06/2003
dc.source.conferencelocationSan Francisco, CA USA
imec.availabilityPublished - imec


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