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A novel low voltage memory device with an engineered SiO2/high-k tunneling barrier

dc.contributor.authorBlomme, Pieter
dc.contributor.authorGovoreanu, Bogdan
dc.contributor.authorVan Houdt, Jan
dc.contributor.authorDe Meyer, Kristin
dc.date.accessioned2021-10-15T04:02:08Z
dc.date.available2021-10-15T04:02:08Z
dc.date.issued2003
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/7224
dc.sourceIIOimport
dc.titleA novel low voltage memory device with an engineered SiO2/high-k tunneling barrier
dc.typeProceedings paper
dc.contributor.imecauthorBlomme, Pieter
dc.contributor.imecauthorGovoreanu, Bogdan
dc.contributor.imecauthorVan Houdt, Jan
dc.contributor.imecauthorDe Meyer, Kristin
dc.contributor.orcidimecVan Houdt, Jan::0000-0003-1381-6925
dc.source.peerreviewno
dc.source.beginpage93
dc.source.endpage94
dc.source.conferenceNon-Volatile Semiconductor Memory Workshop - NVSMW
dc.source.conferencedate16/02/2003
dc.source.conferencelocationMonterey, CA USA
imec.availabilityPublished - imec


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