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A low power high speed parallel concatenated turbo-decoding architecture

dc.contributor.authorBougard, Bruno
dc.contributor.authorGiulietti, Alexandre
dc.contributor.authorDesset, Claude
dc.contributor.authorVan der Perre, Liesbet
dc.contributor.authorCatthoor, Francky
dc.date.accessioned2021-10-15T04:03:38Z
dc.date.available2021-10-15T04:03:38Z
dc.date.issued2003-09
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/7249
dc.sourceIIOimport
dc.titleA low power high speed parallel concatenated turbo-decoding architecture
dc.typeProceedings paper
dc.contributor.imecauthorDesset, Claude
dc.contributor.imecauthorCatthoor, Francky
dc.contributor.orcidimecDesset, Claude::0000-0002-5822-1688
dc.contributor.orcidimecCatthoor, Francky::0000-0002-3599-8515
dc.source.peerreviewno
dc.source.beginpage511
dc.source.endpage514
dc.source.conference3rd International Symposium on Turbo-Codes and Related Topics
dc.source.conferencedate1/09/2003
dc.source.conferencelocationBrest France
imec.availabilityPublished - imec


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