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Simulation of nanofloating gate memory with stacked high-k gate dielectrics

dc.contributor.authorGovoreanu, Bogdan
dc.contributor.authorBlomme, Pieter
dc.contributor.authorVan Houdt, Jan
dc.contributor.authorDe Meyer, Kristin
dc.date.accessioned2021-10-15T04:50:16Z
dc.date.available2021-10-15T04:50:16Z
dc.date.issued2003
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/7627
dc.sourceIIOimport
dc.titleSimulation of nanofloating gate memory with stacked high-k gate dielectrics
dc.typeProceedings paper
dc.contributor.imecauthorGovoreanu, Bogdan
dc.contributor.imecauthorBlomme, Pieter
dc.contributor.imecauthorVan Houdt, Jan
dc.contributor.imecauthorDe Meyer, Kristin
dc.contributor.orcidimecVan Houdt, Jan::0000-0003-1381-6925
dc.source.peerreviewno
dc.source.beginpage299
dc.source.endpage302
dc.source.conferenceIEEE International Conference on Simulation of Semiconductor Processes and Devices - SISPAD
dc.source.conferencedate3/09/2003
dc.source.conferencelocationBoston USA
imec.availabilityPublished - imec


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