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Gate-source-drain architecture impact on DC and performance of sub-100-nm elevated source/drain NMOS transistors

dc.contributor.authorJeamsaksiri, Wutthinan
dc.contributor.authorJurczak, Gosia
dc.contributor.authorGrau, Lluis
dc.contributor.authorLinten, Dimitri
dc.contributor.authorAugendre, Emmanuel
dc.contributor.authorde Potter de ten Broeck, Muriel
dc.contributor.authorRooyackers, Rita
dc.contributor.authorWambacq, Piet
dc.contributor.authorBadenes, Gonçal
dc.date.accessioned2021-10-15T05:01:11Z
dc.date.available2021-10-15T05:01:11Z
dc.date.issued2003
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/7688
dc.sourceIIOimport
dc.titleGate-source-drain architecture impact on DC and performance of sub-100-nm elevated source/drain NMOS transistors
dc.typeJournal article
dc.contributor.imecauthorJurczak, Gosia
dc.contributor.imecauthorLinten, Dimitri
dc.contributor.imecauthorde Potter de ten Broeck, Muriel
dc.contributor.imecauthorWambacq, Piet
dc.contributor.orcidimecLinten, Dimitri::0000-0001-8434-1838
dc.contributor.orcidimecWambacq, Piet::0000-0003-4388-7257
dc.source.peerreviewno
dc.source.beginpage610
dc.source.endpage617
dc.source.journalIEEE Trans. Electron Devices
dc.source.issue3
dc.source.volume50
imec.availabilityPublished - imec


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