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Silicon scaling and its consequences for memory technology

dc.contributor.authorMaes, Herman
dc.contributor.authorVan Houdt, Jan
dc.date.accessioned2021-10-15T05:31:59Z
dc.date.available2021-10-15T05:31:59Z
dc.date.issued2003
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/7843
dc.sourceIIOimport
dc.titleSilicon scaling and its consequences for memory technology
dc.typeProceedings paper
dc.contributor.imecauthorVan Houdt, Jan
dc.contributor.orcidimecVan Houdt, Jan::0000-0003-1381-6925
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage7
dc.source.endpage11
dc.source.conference19th IEEE Nonvolatile Semiconductor Memory Workshop Proceedings
dc.source.conferencedate16/02/2003
dc.source.conferencelocationMonterey, CA USA
imec.availabilityPublished - open access


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