Show simple item record

Exploiting loop-level parallelism on coarse-grained reconfigurable architectures using modulo scheduling

dc.contributor.authorMei, Bingfeng
dc.contributor.authorVernalde, Serge
dc.contributor.authorVerkest, Diederik
dc.contributor.authorDe Man, Hugo
dc.contributor.authorLauwereins, Rudy
dc.date.accessioned2021-10-15T05:40:58Z
dc.date.available2021-10-15T05:40:58Z
dc.date.issued2003
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/7885
dc.sourceIIOimport
dc.titleExploiting loop-level parallelism on coarse-grained reconfigurable architectures using modulo scheduling
dc.typeProceedings paper
dc.contributor.imecauthorVernalde, Serge
dc.contributor.imecauthorVerkest, Diederik
dc.contributor.imecauthorDe Man, Hugo
dc.contributor.imecauthorLauwereins, Rudy
dc.contributor.orcidimecVerkest, Diederik::0000-0001-6567-2746
dc.contributor.orcidimecLauwereins, Rudy::0000-0002-3861-0168
dc.source.peerreviewno
dc.source.beginpage296
dc.source.endpage301
dc.source.conferenceDesign, Automation and Test in Europe Conference and Exhibition - DATE
dc.source.conferencedate3/03/2003
dc.source.conferencelocationMunich Germany
imec.availabilityPublished - imec


Files in this item

FilesSizeFormatView

There are no files associated with this item.

This item appears in the following collection(s)

Show simple item record