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Exploiting loop-level parallelism on coarse-grained reconfigurable architectures using modulo scheduling

dc.contributor.authorMei, Bingfeng
dc.contributor.authorVernalde, Serge
dc.contributor.authorVerkest, Diederik
dc.contributor.authorDe Man, Hugo
dc.contributor.authorLauwereins, Rudy
dc.date.accessioned2021-10-15T05:41:24Z
dc.date.available2021-10-15T05:41:24Z
dc.date.issued2003-09
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/7887
dc.sourceIIOimport
dc.titleExploiting loop-level parallelism on coarse-grained reconfigurable architectures using modulo scheduling
dc.typeJournal article
dc.contributor.imecauthorVernalde, Serge
dc.contributor.imecauthorVerkest, Diederik
dc.contributor.imecauthorDe Man, Hugo
dc.contributor.imecauthorLauwereins, Rudy
dc.contributor.orcidimecVerkest, Diederik::0000-0001-6567-2746
dc.contributor.orcidimecLauwereins, Rudy::0000-0002-3861-0168
dc.source.peerreviewno
dc.source.beginpage255
dc.source.endpage261
dc.source.journalIEE Proceedings: Computer & Digital Techniques
dc.source.issue5
dc.source.volume150
imec.availabilityPublished - imec


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