Show simple item record

Impact of p-well implantation parameters compatible with deep submicron CMOS techology on junction leakage

dc.contributor.authorPoyai, Amporn
dc.contributor.authorRittaporn, Itti
dc.contributor.authorRooyackers, Rita
dc.contributor.authorSimoen, Eddy
dc.contributor.authorClaeys, Cor
dc.date.accessioned2021-10-15T06:14:25Z
dc.date.available2021-10-15T06:14:25Z
dc.date.issued2003
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/8035
dc.sourceIIOimport
dc.titleImpact of p-well implantation parameters compatible with deep submicron CMOS techology on junction leakage
dc.typeProceedings paper
dc.contributor.imecauthorSimoen, Eddy
dc.contributor.orcidimecSimoen, Eddy::0000-0002-5218-4046
dc.source.peerreviewno
dc.source.beginpage1381
dc.source.endpage1385
dc.source.conferenceProceedings of the 26th Electrical Engineering Conference - EECON
dc.source.conferencedate6/11/2003
dc.source.conferencelocationBangkok Thailand
imec.availabilityPublished - imec


Files in this item

FilesSizeFormatView

There are no files associated with this item.

This item appears in the following collection(s)

Show simple item record