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Test circuits for fast and reliable assessment of CDM robustness of I/O stages

dc.contributor.authorStadler, Wolfgang
dc.contributor.authorEsmark, K.
dc.contributor.authorReynders, K.
dc.contributor.authorZuhbeidat, M.
dc.contributor.authorGraf, M.
dc.contributor.authorWilkening, W.
dc.contributor.authorWillemen, J.
dc.contributor.authorQu, S.
dc.contributor.authorSettler, S.
dc.contributor.authorEtherton, M.
dc.contributor.authorNuernbergk, D.
dc.contributor.authorWolf, H.
dc.contributor.authorGieser, H.
dc.contributor.authorSoppa, W.
dc.contributor.authorDe Heyn, Vincent
dc.contributor.authorMahadeva Iyer, Natarajan
dc.contributor.authorGroeseneken, Guido
dc.contributor.authorMorena, E.
dc.contributor.authorStella, R.
dc.contributor.authorAndreini, A.
dc.contributor.authorLitzenberger, M.
dc.contributor.authorPogany, D.
dc.contributor.authorGornik, E.
dc.contributor.authorFoss, C.
dc.contributor.authorKonrad, A.
dc.contributor.authorFrank, M.
dc.date.accessioned2021-10-15T06:48:49Z
dc.date.available2021-10-15T06:48:49Z
dc.date.issued2003
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/8177
dc.sourceIIOimport
dc.titleTest circuits for fast and reliable assessment of CDM robustness of I/O stages
dc.typeProceedings paper
dc.contributor.imecauthorDe Heyn, Vincent
dc.contributor.imecauthorGroeseneken, Guido
dc.source.peerreviewno
dc.source.beginpage319
dc.source.endpage327
dc.source.conferenceProceedings 25th EOS/ESD Symposium
dc.source.conferencedate21/09/2003
dc.source.conferencelocationLas Vegas, NV USA
imec.availabilityPublished - imec


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