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Analysis and optimization of circuit interconnect performance

dc.contributor.authorPeeters, Joris
dc.contributor.authorBeyne, Eric
dc.date.accessioned2021-09-29T13:15:41Z
dc.date.available2021-09-29T13:15:41Z
dc.date.issued1995
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/817
dc.sourceIIOimport
dc.titleAnalysis and optimization of circuit interconnect performance
dc.typeProceedings paper
dc.contributor.imecauthorBeyne, Eric
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage29
dc.source.endpage34
dc.source.conferenceMCM C/Mixed Technologies and Thick Film Sensors; Proceedings of the NATO Advanced Research Workshop on Advances in Multi-Chip Mo
dc.source.conferencedate23/05/1994
dc.source.conferencelocationIslamorada, Florida USA
imec.availabilityPublished - open access


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