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Electrical modeling and simulation of nanoscale MOS devices with a high-permittivity dielectric gate stack

dc.contributor.authorAutran, J.L.
dc.contributor.authorMunteanu, D.
dc.contributor.authorHoussa, Michel
dc.contributor.authorBescond, M.
dc.contributor.authorGarros, X.
dc.contributor.authorLeroux, C.
dc.date.accessioned2021-10-15T12:39:35Z
dc.date.available2021-10-15T12:39:35Z
dc.date.issued2004
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/8502
dc.sourceIIOimport
dc.titleElectrical modeling and simulation of nanoscale MOS devices with a high-permittivity dielectric gate stack
dc.typeProceedings paper
dc.contributor.imecauthorHoussa, Michel
dc.contributor.orcidimecHoussa, Michel::0000-0003-1844-3515
dc.source.peerreviewno
dc.source.beginpageD6.1
dc.source.conferenceIntegration of Advanced Micro- and Nanoelectronic Devices - Critical Issues and Solutions
dc.source.conferencedate12/04/2004
dc.source.conferencelocationSan Francisco, CA USA
imec.availabilityPublished - imec
imec.internalnotesMaterials Research Society Symposium Proceedings; Vol. 811


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