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Finite element analysis of an improved wafer level package using silicone under bump (SUB) layers

dc.contributor.authorGonzalez, Mario
dc.contributor.authorVanden Bulcke, Mathieu
dc.contributor.authorVandevelde, Bart
dc.contributor.authorBeyne, Eric
dc.contributor.authorLee, Yeong
dc.contributor.authorHarkness, Brian
dc.contributor.authorMeynen, Herman
dc.date.accessioned2021-10-15T13:36:43Z
dc.date.available2021-10-15T13:36:43Z
dc.date.issued2004
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/8968
dc.sourceIIOimport
dc.titleFinite element analysis of an improved wafer level package using silicone under bump (SUB) layers
dc.typeProceedings paper
dc.contributor.imecauthorGonzalez, Mario
dc.contributor.imecauthorVanden Bulcke, Mathieu
dc.contributor.imecauthorVandevelde, Bart
dc.contributor.imecauthorBeyne, Eric
dc.contributor.orcidimecVandevelde, Bart::0000-0002-6753-6438
dc.contributor.orcidimecBeyne, Eric::0000-0002-3096-050X
dc.source.peerreviewno
dc.source.beginpage163
dc.source.endpage168
dc.source.conferenceEuroSimE: 5th Int. Conf. on Thermal & Mechanical Simulation and Experiments in Micro-Electronics and Micro-Systems
dc.source.conferencedate10/05/2004
dc.source.conferencelocationBrussels Belgium
imec.availabilityPublished - imec


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