Show simple item record

Evaluation of the channel engineering impact on the analog performance of deep-submicron partially depleted SOI MOSFETs at low temperatures

dc.contributor.authorHayama, K.
dc.contributor.authorOhyama, H.
dc.contributor.authorTakakura, K.
dc.contributor.authorRafi, J.M.
dc.contributor.authorMercha, Abdelkarim
dc.contributor.authorSimoen, Eddy
dc.contributor.authorClaeys, Cor
dc.date.accessioned2021-10-15T13:43:28Z
dc.date.available2021-10-15T13:43:28Z
dc.date.issued2004
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/9002
dc.sourceIIOimport
dc.titleEvaluation of the channel engineering impact on the analog performance of deep-submicron partially depleted SOI MOSFETs at low temperatures
dc.typeProceedings paper
dc.contributor.imecauthorMercha, Abdelkarim
dc.contributor.imecauthorSimoen, Eddy
dc.contributor.orcidimecMercha, Abdelkarim::0000-0002-2174-6958
dc.contributor.orcidimecSimoen, Eddy::0000-0002-5218-4046
dc.source.peerreviewno
dc.source.beginpage21
dc.source.endpage26
dc.source.conferenceMicroelectronics Technology and Devices SBMICRO
dc.source.conferencedate8/09/2004
dc.source.conferencelocationRecife Brazil
imec.availabilityPublished - imec
imec.internalnotesElectrochemical Society Proceedings; Vol. 2004-03


Files in this item

FilesSizeFormatView

There are no files associated with this item.

This item appears in the following collection(s)

Show simple item record