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Sub-1nm EOT scaling for high-k metal-gate stacks

dc.contributor.authorHeyns, Marc
dc.contributor.authorSchram, Tom
dc.contributor.authorRagnarsson, Lars-Ake
dc.contributor.authorDe Gendt, Stefan
dc.contributor.authorKerber, Andreas
dc.date.accessioned2021-10-15T13:49:39Z
dc.date.available2021-10-15T13:49:39Z
dc.date.issued2004
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/9030
dc.sourceIIOimport
dc.titleSub-1nm EOT scaling for high-k metal-gate stacks
dc.typeJournal article
dc.contributor.imecauthorHeyns, Marc
dc.contributor.imecauthorSchram, Tom
dc.contributor.imecauthorRagnarsson, Lars-Ake
dc.contributor.imecauthorDe Gendt, Stefan
dc.contributor.orcidimecRagnarsson, Lars-Ake::0000-0003-1057-8140
dc.contributor.orcidimecDe Gendt, Stefan::0000-0003-3775-3578
dc.source.peerreviewno
dc.source.beginpage22
dc.source.journalSolid State Technology
dc.source.issue7
dc.source.volume47
imec.availabilityPublished - imec


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