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L0 cluster synthesis and operation shuffling

dc.contributor.authorJayapala, Murali
dc.contributor.authorVander Aa, Tom
dc.contributor.authorBarat, F.
dc.contributor.authorCatthoor, Francky
dc.contributor.authorCorporaal, Henk
dc.contributor.authorDeconinck, G.
dc.date.accessioned2021-10-15T14:02:46Z
dc.date.available2021-10-15T14:02:46Z
dc.date.issued2004-09
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/9092
dc.sourceIIOimport
dc.titleL0 cluster synthesis and operation shuffling
dc.typeProceedings paper
dc.contributor.imecauthorJayapala, Murali
dc.contributor.imecauthorVander Aa, Tom
dc.contributor.imecauthorCatthoor, Francky
dc.contributor.orcidimecJayapala, Murali::0000-0001-7917-0149
dc.contributor.orcidimecVander Aa, Tom::0000-0002-1504-5266
dc.contributor.orcidimecCatthoor, Francky::0000-0002-3599-8515
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage311
dc.source.endpage321
dc.source.conferenceIntegrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation - PATMOS
dc.source.conferencedate15/09/2004
dc.source.conferencelocationSantorini Greece
imec.availabilityPublished - open access
imec.internalnotesLecture Notes in Computer Science; Vol. 3254


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