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SPER junction optimisation in 45nm CMOS devices

dc.contributor.authorLindsay, Richard
dc.contributor.authorSeveri, Simone
dc.contributor.authorPawlak, Bartek
dc.contributor.authorHenson, Kirklen
dc.contributor.authorLauwers, Anne
dc.contributor.authorPagès, Xavier
dc.contributor.authorSatta, Alessandra
dc.contributor.authorSurdeanu, Radu
dc.contributor.authorLendzian, H.
dc.contributor.authorMaex, Karen
dc.date.accessioned2021-10-15T14:29:04Z
dc.date.available2021-10-15T14:29:04Z
dc.date.issued2004
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/9207
dc.sourceIIOimport
dc.titleSPER junction optimisation in 45nm CMOS devices
dc.typeMeeting abstract
dc.contributor.imecauthorSeveri, Simone
dc.contributor.imecauthorPawlak, Bartek
dc.contributor.imecauthorLauwers, Anne
dc.contributor.imecauthorMaex, Karen
dc.source.peerreviewno
dc.source.beginpage70
dc.source.endpage75
dc.source.conferenceExtended Abstracts of the 4th International Workshop on Junction Technology
dc.source.conferencedate15/03/2004
dc.source.conferencelocationShangai China
imec.availabilityPublished - imec


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