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Comparison between drain induced barrier lowering in partially and fully depleted 0.13 μm SOI nMOSFETs in low temperature operation

dc.contributor.authorPavanello, M.A.
dc.contributor.authorMartino, J.A.
dc.contributor.authorSimoen, Eddy
dc.contributor.authorClaeys, Cor
dc.date.accessioned2021-10-15T15:22:10Z
dc.date.available2021-10-15T15:22:10Z
dc.date.issued2004
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/9409
dc.sourceIIOimport
dc.titleComparison between drain induced barrier lowering in partially and fully depleted 0.13 μm SOI nMOSFETs in low temperature operation
dc.typeProceedings paper
dc.contributor.imecauthorSimoen, Eddy
dc.contributor.orcidimecSimoen, Eddy::0000-0002-5218-4046
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage105
dc.source.endpage111
dc.source.conferenceProceedings WOLTE-6 - 6th European Workshop on Low Temperature Electronics
dc.source.conferencedate23/06/2004
dc.source.conferencelocationNoordwijk The Netherlands
imec.availabilityPublished - imec


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