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A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs

dc.contributor.authorResano Ezcaray, Jesús Javier
dc.contributor.authorVerkest, Diederik
dc.contributor.authorMozos, Daniel
dc.contributor.authorVernalde, Serge
dc.contributor.authorCatthoor, Francky
dc.date.accessioned2021-10-15T15:48:43Z
dc.date.available2021-10-15T15:48:43Z
dc.date.issued2004
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/9506
dc.sourceIIOimport
dc.titleA hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs
dc.typeJournal article
dc.contributor.imecauthorVerkest, Diederik
dc.contributor.imecauthorVernalde, Serge
dc.contributor.imecauthorCatthoor, Francky
dc.contributor.orcidimecVerkest, Diederik::0000-0001-6567-2746
dc.contributor.orcidimecCatthoor, Francky::0000-0002-3599-8515
dc.source.peerreviewno
dc.source.beginpage291
dc.source.endpage301
dc.source.journalMicroprocessors and microsystems
dc.source.issue5_6
dc.source.volume28
imec.availabilityPublished - imec


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