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Tunnelling 1/fy noise in 5nm HfO2/2.1 nm SiO2 gate stack n-MOSFETs

dc.contributor.authorSimoen, Eddy
dc.contributor.authorMercha, Abdelkarim
dc.contributor.authorPantisano, Luigi
dc.contributor.authorClaeys, Cor
dc.contributor.authorYoung, Edward
dc.date.accessioned2021-10-15T16:17:36Z
dc.date.available2021-10-15T16:17:36Z
dc.date.issued2004
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/9607
dc.sourceIIOimport
dc.titleTunnelling 1/fy noise in 5nm HfO2/2.1 nm SiO2 gate stack n-MOSFETs
dc.typeProceedings paper
dc.contributor.imecauthorSimoen, Eddy
dc.contributor.imecauthorMercha, Abdelkarim
dc.contributor.orcidimecSimoen, Eddy::0000-0002-5218-4046
dc.contributor.orcidimecMercha, Abdelkarim::0000-0002-2174-6958
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage31
dc.source.endpage37
dc.source.conferenceULIS - 5th European Workshop on ULtimate Integration of Silicon
dc.source.conferencedate11/03/2004
dc.source.conferencelocationLeuven Belgium
imec.availabilityPublished - open access


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