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Cleaning of metal gate stacks for the sub 90nm technology node

dc.contributor.authorSnow, Jim
dc.contributor.authorKraus, Harald
dc.contributor.authorVermeyen, Kenneth
dc.contributor.authorFyen, Wim
dc.contributor.authorMertens, Paul
dc.contributor.authorKovacs, Frederic
dc.date.accessioned2021-10-15T16:20:18Z
dc.date.available2021-10-15T16:20:18Z
dc.date.issued2004
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/9616
dc.sourceIIOimport
dc.titleCleaning of metal gate stacks for the sub 90nm technology node
dc.typeProceedings paper
dc.contributor.imecauthorMertens, Paul
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage393
dc.source.endpage399
dc.source.conferenceCleaning Technology in Semiconductor Device Manufacturing VIII. Proceedings of the International Symposium
dc.source.conferencedate12/10/2003
dc.source.conferencelocationOrlando, FL USA
imec.availabilityPublished - open access
imec.internalnotesElectrochemical Society Proceedings; Vol. 2003-26


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