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Time-energy design space exploration for multi-layer memory architectures

dc.contributor.authorSzymanek, R.
dc.contributor.authorCatthoor, Francky
dc.contributor.authorKuchcinski, K.
dc.date.accessioned2021-10-15T16:32:12Z
dc.date.available2021-10-15T16:32:12Z
dc.date.issued2004
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/9656
dc.sourceIIOimport
dc.titleTime-energy design space exploration for multi-layer memory architectures
dc.typeProceedings paper
dc.contributor.imecauthorCatthoor, Francky
dc.contributor.orcidimecCatthoor, Francky::0000-0002-3599-8515
dc.source.peerreviewno
dc.source.beginpage318
dc.source.endpage323
dc.source.conferenceProceedings 7th ACM/IEEE Design and Test in Europe Conference - DATE
dc.source.conferencedate15/02/2004
dc.source.conferencelocationParis France
imec.availabilityPublished - imec


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