Show simple item record

A global bus power optimization methodology for physical design of memory dominated systems by coupling bus segmentation and activity driven block placement

dc.contributor.authorWang, Hua
dc.contributor.authorPapanikolaou, Antonis
dc.contributor.authorMiranda, Miguel
dc.contributor.authorCatthoor, Francky
dc.date.accessioned2021-10-15T17:48:54Z
dc.date.available2021-10-15T17:48:54Z
dc.date.issued2004
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/9899
dc.sourceIIOimport
dc.titleA global bus power optimization methodology for physical design of memory dominated systems by coupling bus segmentation and activity driven block placement
dc.typeProceedings paper
dc.contributor.imecauthorCatthoor, Francky
dc.contributor.orcidimecCatthoor, Francky::0000-0002-3599-8515
dc.source.peerreviewyes
dc.source.beginpage759
dc.source.endpage761
dc.source.conferenceProceedings Asia and South Pacific Design Automation Conference - ASP-DAC
dc.source.conferencedate27/01/2004
dc.source.conferencelocationYokohama Japan
imec.availabilityPublished - imec


Files in this item

FilesSizeFormatView

There are no files associated with this item.

This item appears in the following collection(s)

Show simple item record