Browsing by Author "Benini, Luca"
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Publication 3D Partitioning with Pipeline Optimization for Low-Latency Memory Access in Many-Core SoCs
Proceedings paper2024, IEEE International Symposium on Circuits and Systems (ISCAS), MAY 19-22, 2024Publication An integrated hardware/software approach for run-time scratchpad management
Proceedings paper2004, Proceedings of the 41st Annual Conference on Design Automation, 7/06/2004, p.238-243Publication Applications of computation-in-memory architecture based on memristive devices
Proceedings paper2019, 22nd ACM/IEEE Design and Test in Europe Conference and Exhibition (DATE), 1/03/2019, p.486-491Publication Automatic synthesis of near-threshold circuits with fine-grained performance tunability
Publication Bandwidth-Latency-Thermal Co-Optimization of Interconnect-Dominated Many-Core 3D-IC
Journal article2025, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, (33) 2, p.346-357Publication Fast and power efficient dynamic data-layout with DMA-capable memories
Proceedings paper2004, 1st International Workshop on Power-Aware Real-Time Computing - PARC, 26/09/2004, p.1-4Publication Hier-3D: A Methodology for Physical Hierarchy Exploration of 3-D ICs
Journal article2024, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, (43) 7, p.1957-1970Publication HTVM: Efficient Neural Network Deployment On Heterogeneous TinyML Platforms
Proceedings paper2023, 60th ACM/IEEE Design Automation Conference (DAC), JUL 09-13, 2023Publication MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration
Publication System-level power/performance evaluation of 3D stacked DRAMs for mobile applications
Proceedings paper2009, Design, Automation and Test in Europe Conference - DATE, 20/04/2009, p.923-928