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3D Partitioning with Pipeline Optimization for Low-Latency Memory Access in Many-Core SoCs
Publication:
3D Partitioning with Pipeline Optimization for Low-Latency Memory Access in Many-Core SoCs
Date
2024
Proceedings Paper
https://doi.org/10.1109/ISCAS58744.2024.10558687
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APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Das, Sudipta
;
Riedel, Samuel
;
Bertuletti, Marco
;
Benini, Luca
;
Brunion, Moritz
;
Ryckaert, Julien
;
Myers, James
;
Biswas, Dwaipayan
;
Milojevic, Dragomir
Journal
N/A
Abstract
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569
since deposited on 2024-09-21
Acq. date: 2025-10-25
Citations
Metrics
Views
569
since deposited on 2024-09-21
Acq. date: 2025-10-25
Citations