Browsing by Author "Berekovic, Mladen"
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Publication A low-power ASIP for IEEE 802.15.4a ultra-wideband impulse radio baseband processing
Proceedings paper2009, Design, Automation and Test in Europe Conference - DATE, 20/04/2009, p.1614-1619Publication ADRES & DRESC: architecture and compiler for coarse-grain reconfigurable processors
Publication Architecture enhancements for the ADRES coarse-grained reconfigurable array
Publication C-programmable coarse grain processor with breakthrough power efficiency enables the next generation multi-mode nomadic embedded devices
Proceedings paper2005, GSPx 2005 Pervasive Signal Processing, 24/10/2005Publication Design of 100 μW wireless sensor nodes for biomedical monitoring
Publication EDA role in the design-technology co-optimization towards N7
Proceedings paper2016, CDNLive Cadence User Conference EMEA, 2/05/2016Publication Interconnect power analysis for a coarse-grained reconfigurable array processor
Proceedings paper2008-09, International Workshop on Power and Timing Modeling, Optimization and Simulation - PATMOS, 10/09/2008Publication IR-drop aware design and Technology co-optimization for N5 node with different device and cell height options
Proceedings paper2017, IEEE/ACM International Conference on Computer-Aided Design - ICCAD, 18/06/2017, p.89-94Publication Low-power ASIP architecture exploration and optimization for Reed-Solomon processing
Proceedings paper2009, 20th IEEE International Conference on Application-Specific Systems, Architectures and Processors - ASAP, 7/07/2009, p.177-182Publication Mapping and design space exploration of the AES cryptographic algorithm on a coarse-grain reconfigurable array processor
Proceedings paper2008, 19th IEEE International Conference on Application-specific Systems, Architectures and Processors - ASAP, 2/07/2008, p.251-256Publication Mapping control-intensive video kernels onto a coarse-grain reconfigurable architecture: the H.264/AVC deblocking filter
Publication Mapping of video compression algorithms on the ADRES coarse-Ggrain reconfigurable array
Berekovic, MladenProceedings paper2005-11, MSP7 Workshop on Multimedia and Stream Processors, 11/11/2005Publication Still image processing on coarse-grained reconfigurable array architectures
Journal article2010, Journal of Signal Processing Systems, 60, p.225-237Publication Still image processing on coarse-grained reconfigurable array architectures
Proceedings paper2007-10, IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia - ESTIMedia, 4/10/2007, p.67-72Publication Towards the implementation of a baseline H.264/AVC decoder onto a reconfigurable architecture