Browsing by Author "Chae, Jung Kyu"
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Publication CFET standard-cell design down to 3Track height for node 3nm and below
Proceedings paper2019, Design-Process-Technology Co-optimization for Manufacturability XIII, 24/02/2019, p.1096206Publication Track height reduction for standard-cell in below 5nm node: How low can you go?
Meeting abstract2018, Design-Process-Technology Co-optimization for Manufacturability XII, 25/02/2018, p.1058809