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CFET standard-cell design down to 3Track height for node 3nm and below
Publication:
CFET standard-cell design down to 3Track height for node 3nm and below
Date
2019
Proceedings Paper
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41268.pdf
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APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Sherazi, Yasser
;
Chae, Jung Kyu
;
Debacker, Peter
;
Mattii, Luca
;
Verkest, Diederik
;
Mocuta, Anda
;
Kim, Ryan Ryoung han
;
Spessot, Alessio
;
Dounde, Amit
;
Ryckaert, Julien
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1
since deposited on 2021-10-27
Acq. date: 2025-10-23
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2099
since deposited on 2021-10-27
Acq. date: 2025-10-23
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Downloads
1
since deposited on 2021-10-27
Acq. date: 2025-10-23
Views
2099
since deposited on 2021-10-27
Acq. date: 2025-10-23
Citations