Publication:

CFET standard-cell design down to 3Track height for node 3nm and below

Date

2019
Proceedings Paper
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dc.contributor.authorSherazi, Yasser
dc.contributor.authorChae, Jung Kyu
dc.contributor.authorDebacker, Peter
dc.contributor.authorMattii, Luca
dc.contributor.authorVerkest, Diederik
dc.contributor.authorMocuta, Anda
dc.contributor.authorKim, Ryan Ryoung han
dc.contributor.authorSpessot, Alessio
dc.contributor.authorDounde, Amit
dc.contributor.authorRyckaert, Julien
dc.contributor.imecauthorSherazi, Yasser
dc.contributor.imecauthorDebacker, Peter
dc.contributor.imecauthorVerkest, Diederik
dc.contributor.imecauthorKim, Ryan Ryoung han
dc.contributor.imecauthorSpessot, Alessio
dc.contributor.imecauthorDounde, Amit
dc.contributor.imecauthorRyckaert, Julien
dc.contributor.orcidimecDebacker, Peter::0000-0003-3825-5554
dc.contributor.orcidimecVerkest, Diederik::0000-0001-6567-2746
dc.date.accessioned2021-10-27T18:06:33Z
dc.date.available2021-10-27T18:06:33Z
dc.date.embargo9999-12-31
dc.date.issued2019
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/33986
dc.identifier.urlhttps://doi.org/10.1117/12.2514571
dc.source.beginpage1096206
dc.source.conferenceDesign-Process-Technology Co-optimization for Manufacturability XIII
dc.source.conferencedate24/02/2019
dc.source.conferencelocationSan Jose, CA USA
dc.title

CFET standard-cell design down to 3Track height for node 3nm and below

dc.typeProceedings paper
dspace.entity.typePublication
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