imec Institutional Repository Browsing {{ collection }} by Author "Cline, B."

Publication

Buried Bitline for sub-5nm SRAM Design

Mathur, R.

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Bhargava, M.

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Annamalai, S.

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Chong, Y. K.

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Sinha, S.

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Cline, B.

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Kulkarni, J. P.

Proceedings paper

2020, IEEE International Electron Devices Meeting (IEDM), DEC 12-18, 2020

Publication

Buried Interconnects for Sub-5 nm SRAM Design

Mathur, R.

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Bhargava, M.

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Cline, B.

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Journal article

2022, IEEE TRANSACTIONS ON ELECTRON DEVICES, (69) 3, p.1041-1047

Publication

Buried power rails and back-side power grids: ARM CPU power delivery network design beyond 5nm

Prasad, D.

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Nibhanupudi, S.

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Das, S.

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Proceedings paper

2019, IEEE International Electron Devices Meeting - IEDM 2019, 9/12/2019, p.446-449

Browsing by Author "Cline, B."