Browsing by Author "Dey, Bappaditya"
- Results Per Page
- Sort Options
Publication A Comparative Study of Deep-Learning Object Detectors for Semiconductor Defect Detection
Proceedings paper2022, 29th IEEE International Conference on Electronics, Circuits and Systems (IEEE ICECS), OCT 24-26, 2022Publication A Machine Learning Approach Towards SKILL Code Autocompletion
Proceedings paper2024, Conference on DTCO and Computational Patterning III, FEB 26-29, 2024, p.Art. 129540RPublication A novel design gate based low-cost configurable RO PUF using reversible logic
Proceedings paper2019, 2019 IEEE 62nd International Midwest Symposium on Circuits and Systems, 4/08/2019Publication A Novel Design Reversible logic based Configurable Fault-Tolerant Embryonic Hardware
Proceedings paper2020, IEEE International Symposium on Circuits and Systems (ISCAS), OCT 10-21, 2020Publication A novel reconfigurable hardware architecture of neural network
Proceedings paper2019, 2019 IEEE 62nd International Midwest Symposium on Circuits and Systems, 4/08/2019Publication A reversible-logic based architecture for artificial neural network
Proceedings paper2020, 63rd IEEE International Midwest Symposium on Circuits and Systems, 9/08/2020Publication A Reversible-Logic based Architecture for Convolutional Neural Network (CNN)
Proceedings paper2021, IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), AUG 09-11, 2021, p.1070-1073Publication A Reversible-Logic based Architecture for Long Short-Term Memory (LSTM) Network
Proceedings paper2021, IEEE International Symposium on Circuits and Systems (IEEE ISCAS), MAY 22-28, 2021Publication A Reversible-Logic based Architecture for VGGNet
Proceedings paper2021, 28th IEEE International Conference on Electronics, Circuits, and Systems (IEEE ICECS), NOV 28-DEC 01, 2021Publication Adaptive Hardware Architecture for Neural-Network-on-Chip
Proceedings paper2022, IEEE 65th International Midwest Symposium on Circuits and Systems (MWSCAS), AUG 07-10, 2022Publication An Efficient Embryonic Hardware Architecture based on Network-on-Chip
Proceedings paper2021, IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), AUG 09-11, 2021, p.449-452Publication An Efficient Reconfigurable Neural Network on Chip
Proceedings paper2021, 28th IEEE International Conference on Electronics, Circuits, and Systems (IEEE ICECS), NOV 28-DEC 01, 2021Publication Architecture of a novel low-cost hardware neural network
Proceedings paper2020, 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS), 9/08/2020Publication BEOL N2: M2 through SAxP process from MP21 to MP26: 193i SAQP vs EUV SADP
Proceedings paper2023-04-28, Conference on Optical and EUV Nanolithography XXXVI Part of SPIE Advanced Lithography and Patterning Conference, 23/02/2023Publication Code Generation Using Machine Learning: A Systematic Review
Journal article review2022, IEEE ACCESS, (10) IEEE Access, vol. 10, pp. 82434-82455, 2022, doi: 10.1109/ACCESS.2022.3196347, p.82434-82455Publication e-beam metrology of thin resist for high NA EUVL
; ; ; ; ; Journal article review2023, JAPANESE JOURNAL OF APPLIED PHYSICS, (62) SG, p.Art. SG0808Publication EUV mask defect inspection for the 3nm technology node
Proceedings paper2023, 38th European Mask and Lithography Conference (EMLC 2023), 17/06/2023, p.Art. 128020HPublication Extraction of Roughness Measurements from Thin Resists with Low Signal-to-Noise-Ratio (SNR) SEM Images by Applying Deep Learning Denoiser
Proceedings paper2022, International Conference on Extreme Ultraviolet Lithography, SEP 26-29, 2022, p.1229201Publication Machine Learning-Based Edge Placement Error Analysis and Optimization: A Systematic Review
Journal article review2023, IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, (36) 1, p.1-13Publication Neuro-NoC: Energy Optimization in Heterogeneous Many-Core NoC using Neural Networks in Dark Silicon Era