Browsing by Author "Ervin, Joseph"
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Publication CMOS area scaling and the need for high aspect ratio vias
Proceedings paper2018, 50th International Conference on Solid State Devices and Materials - SSDM, 9/09/2018, p.453-454Publication Evaluation of the impact of source/drain epi implementation on logic performance using combined process and circuit simulation
Proceedings paper2020, International Conference on Solid State Devices and Materials - SSDM 2020, 27/09/2020, p.A-5-03Publication Impact of EUV resist thickness on local critical dimension uniformities for sub-30 nm CD Via Patterning
Proceedings paper2020, Extreme Ultraviolet (EUV) Lithography XI, part of SPIE Advanced Lithography, 23/02/2020, p.1132326Publication Self-aligned block and fully self-aligned via for iN5 Metal 2 Self-aligned quadruple patterning
Proceedings paper2018, Extreme Ultraviolet (EUV) Lithography IX, 25/02/2018, p.105830WPublication Self-aligned block and fully self-aligned via for iN5 metal 2 self-aligned quadruple patterning
Proceedings paper2018, Extreme Ultraviolet (EUV) Lithography IX, 25/02/2018, p.105830W