Browsing by Author "Goossens, Gert"
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Publication A generalized state assignment theory for transformations on sgnal transition graphs
Journal article1994, Journal of VLSI Signal Processing, 7, p.101-115Publication A graph-based processor model for retargetable code generation
Proceedings paper1996, European Design and Test Conference - ED&TC 96, 11/03/1996, p.102-107Publication A unified scheduling model for high-level synthesis and code generation
Proceedings paper1995, Proceedings of the European Design and Test Conference. ED&TC 1995; March 6-9, 1995; Paris., p.234-238Publication Bit-Alignment for Retargetable Code Generators
Proceedings paper1994, 7th International Symposium on High Level Synthesis, 18/05/1994, p.76-81Publication Data Routing: A Paradigm for Efficient Data-Path Synthesis and Code Generation
Proceedings paper1994, 7th ACM/IEEE International Symposium on High Level Synthesis, 18/05/1994, p.17-20Publication Design of heterogeneous ICs for mobile and personal communciation systems
Proceedings paper1994, IEEE/ACM International Conference on Computer-Aided Design - ICCAD. Digest of Technical Papers, 6/11/1994, p.524-531Publication Embedded software in real-time signal processing systems: application and architecture trends
Publication Embedded software in real-time signal processing systems: design technologies
Publication Formalisation of multi-precision arithmetic for high-level synthesis of DSP architectures
Journal article1995, Journal of VLSI Signal Processing, 11, p.97-112Publication Guest editorial introduction to the special issue on the eighth IEEE international symposium on system synthesis
Publication Instruction Set Definition and Instruction Selection for ASIPs
Proceedings paper1994, 7th International Symposium on High Level Synthesis, 18/05/1994, p.11-16Publication Integration of medium-throughput signal processing algorithms on flexible instruction-set architectures
Publication Modeling and synthesis of timed asynchronous circuits
Proceedings paper1994, Proceedings European Design Automation Conference (EURODAC) with EURO-VHDL '94, 19/09/1994, p.460-465Publication Modelling hardware-specific data-types for simulation and compilation in HW/SW co-design
Proceedings paper1996, SASIMI '96 : Synthesis and System Integration of Mixed Technologies, 25/11/1996, p.255-262Publication Multi-thread graph: a system model for real-time embedded software synthesis
Proceedings paper1997, Proceedings European Design & Test Conference - ED&TC, 17/03/1997, p.476-481Publication Optimal Scheduling and Software Pipelining of Repetitive Signal Flow Graphs with Delay Line Optimization
Proceedings paper1994, Proceedings European Design and Test Conference - EDTC, 28/02/1994, p.490-494Publication Processor modeling and code selection for retargetable compilation
Publication Programmable chips in consumer electronics and telecommunications
Publication Real-time multi-tasking in software synthesis for information processing systems
Proceedings paper1995, Proceedings of the 8th International Symposium on System Synthesis; 13-15 Sept. 1995; Cannes, France., 13/09/1995, p.48-53Publication Scheduling with Register Constraints for DSP Architectures
Journal article1994, Integration, The VLSI Journal, 18, p.95-120