Browsing by Author "Hamdioui, Said"
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Publication 2-output Spin Wave Programmable Logic Gate
Proceedings paper2020, 19th IEEE-Computer-Society Annual Symposium on VLSI (ISVLSI), JUL 06-08, 2020, p.60-65Publication 3D-COSTAR: A cost model for 3D stacked ICs
Oral presentation2013, Friday Workshop on 3D Integration at Design, Automation and Test in Europe - DATEPublication 3D-COSTAR: A cost model for 3D-SICs
Proceedings paper2012-11, IEEE International Workshop on Testing Three-Dimensional Stacked ICs - 3D-TEST, 8/11/2012Publication 3D-COSTAR: A cost model for 3D-SICs
Proceedings paper2012-12, 3-D Architectures for Semiconductor Integration and Packaging - 3D-ASIP, 12/12/2012Publication 3D-COSTAR: A tool for 2.5D/3D test flow optimization
Proceedings paper2015-10, IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits - 3D-TEST, 8/10/2015Publication 4-output Programmable Spin Wave Logic Gate
Proceedings paper2020, 38th IEEE International Conference on Computer Design (ICCD), OCT 18-21, 2020, p.332-335Publication A Classification of Memory-Centric Computing
Publication A DfT architecture and tool flow for 3D-SICs with test data compression, embedded cores, and multiple towers
Journal article2015, IEEE Design & Test, (32) 4, p.40-48Publication A Spin Wave Based Approximate 4:2 Compressor Seeking the most energy-efficient digital computing paradigm
Journal article2022, IEEE NANOTECHNOLOGY MAGAZINE, (16) 1, p.47-56Publication A Survey on Memory-centric Computer Architectures
Publication Achieving Wave Pipelining in Spin Wave Technology
Proceedings paper2021, 22nd International Symposium on Quality Electronic Design (ISQED), APR 07-09, 2021, p.54-59Publication Applications of computation-in-memory architecture based on memristive devices
Proceedings paper2019, 22nd ACM/IEEE Design and Test in Europe Conference and Exhibition (DATE), 1/03/2019, p.486-491Publication Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers
Proceedings paper2013-05, IEEE European Test Symposium - ETS, 27/05/2013, p.15-20Publication Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers
Oral presentation2013, Cadence CDNLive! EMEAPublication Bias temperature instability analysis in SRAM decoder
Proceedings paper2013, 18th IEEE European Test Symposium - ETS, 27/05/2013, p.1Publication Bias temperature instability analysis of FinFET based SRAM cells
Proceedings paper2014, Design, Automation and Test in Europe Conference - DATE, 24/03/2014, p.1-6Publication BTI analysis for high performance and low power SRAM sense amplifier designs
Proceedings paper2015, 4th MEDIAN Project Workshop (organised as a DATE 2015 Friday Workshop), 1/03/2015Publication BTI impact on logical gates in nano-scale CMOS technology
Proceedings paper2012, IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems - DDECS, 18/04/2012Publication Characterization and Fault Modeling of Intermediate State Defects in STT-MRAM
Proceedings paper2021, Design, Automation and Test in Europe Conference and Exhibition (DATE), FEB 01-05, 2021, p.1717-1722