Browsing by Author "Kuijk, Maarten"
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Publication 40% efficient thin-film surface-textured light-emitting diodes by optimization of natural lithography
Journal article2000, IEEE Trans. Electron Devices, (47) 7, p.1492-1498Publication 8 x 8 array of cascadable differential pairs of optical thyristors for parallel optical interconnects
Journal article1995, IEEE Trans. Electron Devices, 42, p.2056-2061Publication 8X8 array of cascadable optical thyristor devices for free-space parallel optical interconnects
Proceedings paper1994, Technical Digest International Electron Devices Meeting 1994 - IEDM, 11/12/1994, p.575-8Publication A 2.2 mW 1.75 GS/s 5 bit folding flash ADC in 90 nm digital CMOS
Journal article2009, IEEE Journal of Solid-State Circuits, (44) 3, p.874-882Publication A 2.2mW 5b 1.75GS/s folding flash ADC in 90nm digital CMOS
Proceedings paper2008-02, IEEE International Solid-State Circuits Conference - ISSCC, 3/02/2008, p.252-253Publication A 2.6 mW 6 bit 2.2 GS/s fully dynamic pipeline ADC in 40 nm Digital CMOS
Journal article2010, IEEE Journal of Solid-State Circuits, (45) 10, p.2080-2090Publication A 2.6mW 6b 2.2GS/s 4-times interleaved fully-dynamic pipelined ADC in 40nm digital CMOS
Proceedings paper2010, IEEE International Solid-State Circuits Conference - ISSCC, 7/02/2010, p.296-297Publication A 400uW, 4.7-6.4GHz VCO under an above-IC inductor in 45nm CMOS
Proceedings paper2008-02, IEEE International Solid-State Circuits Conference - ISSCC, 3/02/2008, p.536-537Publication A 400μW, 4.7-6.4GHz 45nm VCO under an above-IC inductor in 45nm CMOS
Proceedings paper2008, 58th Electronic Components abd Technology Conference - ECTC, 27/05/2008, p.164-168Publication A 42 mW 200 fs-jitter 60 GHz sub-sampling PLL in 40 nm CMOS
Journal article2015, IEEE Journal of Solid-State Circuits, (50) 9, p.2025-2036Publication A 42mW 230fs-jitter sub-sampling 60GHz PLL in 40nm CMOS
Proceedings paper2014, IEEE International Solid-State Circuits Conference - ISSCC, 9/02/2014, p.366-367Publication A 42mW wideband baseband receiver section with beamforming functionality for 60GHz applications in 40nm low-power CMOS
Proceedings paper2012, IEEE Radio Frequency Integrated Circuits Symposium - RFIC, 17/06/2012, p.261-264Publication A 5 kV HBM transformer-based ESD protected 5-6 GHz LNA
Proceedings paper2007-06, Symposium on VLSI Circuits. Digest of Technical Papers, 14/06/2007, p.100-101Publication A 6.5-kV ESD protected 3-5-GHz ultra-wideband BiCMOS low noise amplifier using interstage gain roll-off compensation
Proceedings paper2005-09, Proceedings of the IEEE International Conference on Ultra-Wideband, 5/09/2005, p.525-529Publication A 7.6 mW 1.75 GS/s 5 bit flash A/D converter in 90 nm digital CMOS
Proceedings paper2008, IEEE Symposium on VLSI Circuits, 18/06/2008, p.14-15Publication A 900-Mbit/s CMOS data recovery DLL using half-frequency clock
;Maillard, Xavier ;Kuijk, MaartenDevisch, FrédéricJournal article2002, IEEE Journal of Solid-State Circuits, (27) 6, p.711-715Publication A bondpad-size narrowband LNA for digital CMOS
Proceedings paper2007-06, IEEE Radio Frequency Integrated Circuits Symposium - RFIC, 3/06/2007, p.677-680Publication A compact wideband front-end using a single-inductor dual-band VCO in 90 nm digital CMOS
;Borremans, Jonathan ;Bevilacqua, Andrea ;Bronckers, Stephane ;Dehan, MorinKuijk, MaartenJournal article2008, IEEE Journal of Solid-State Circuits, (43) 12, p.2693-2705Publication A fully integrated 7.3 kV HBM ESD-protected transformer-Based 4.5-6 GHz CMOS LNA
Journal article2009, IEEE Journal of Solid-State Circuits, (44) 2, p.344-353Publication A hybridized optical thyristor - CMOS receiver for optoelectronic applications
Journal article1997, IEEE Photonics Technology Letters, 9, p.669-671