Publication:

A 42 mW 200 fs-jitter 60 GHz sub-sampling PLL in 40 nm CMOS

Date

Loading...
Thumbnail Image

Abstract

Description

Statistics

Views

1996 since deposited on 2021-10-22
3last month
Acq. date: 2026-05-16

Citations

Statistics

Views

1996 since deposited on 2021-10-22
3last month
Acq. date: 2026-05-16

Citations