Browsing by Author "Kumar, Ashok"
Now showing 1 - 7 of 7
- Results Per Page
- Sort Options
Publication A Novel Design Reversible logic based Configurable Fault-Tolerant Embryonic Hardware
Proceedings paper2020, IEEE International Symposium on Circuits and Systems (ISCAS), OCT 10-21, 2020Publication A Reversible-Logic based Architecture for Convolutional Neural Network (CNN)
Proceedings paper2021, IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), AUG 09-11, 2021, p.1070-1073Publication A Reversible-Logic based Architecture for Long Short-Term Memory (LSTM) Network
Proceedings paper2021, IEEE International Symposium on Circuits and Systems (IEEE ISCAS), MAY 22-28, 2021Publication A Reversible-Logic based Architecture for VGGNet
Proceedings paper2021, 28th IEEE International Conference on Electronics, Circuits, and Systems (IEEE ICECS), NOV 28-DEC 01, 2021Publication Adaptive Hardware Architecture for Neural-Network-on-Chip
Proceedings paper2022, IEEE 65th International Midwest Symposium on Circuits and Systems (MWSCAS), AUG 07-10, 2022Publication An Efficient Embryonic Hardware Architecture based on Network-on-Chip
Proceedings paper2021, IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), AUG 09-11, 2021, p.449-452Publication An Efficient Reconfigurable Neural Network on Chip
Proceedings paper2021, 28th IEEE International Conference on Electronics, Circuits, and Systems (IEEE ICECS), NOV 28-DEC 01, 2021