Browsing by Author "Lee, Jaehyun"
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Publication Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation--Part I: CNFET Transistor Optimization
Journal article2022, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, (30) 4, p.432-439Publication Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation--Part II: CNT Interconnect Optimization
Journal article2022, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, (30) 4, p.440-448Publication Design Technology Co-Optimization for the DRAM Cell Structure With Contact Resistance Variation
Journal article2024, IEEE TRANSACTIONS ON ELECTRON DEVICES, (71) 3, p.1893-1899