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Browsing by Author "Moroz, V."

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    3D technology roadmap and status

    Marchal, Pol
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    Van der Plas, Geert  
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    Eneman, Geert  
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    Moroz, V.
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    Badaroglu, Mustafa  
    Proceedings paper
    2011, IEEE International Interconnect Technology Conference and Materials for Advanced Metallization - IITC/MAM, 8/05/2011
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    Analysis of microbump induced stress effects in 3D stacked IC technologies

    Ivankovic, Andrej
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    Van der Plas, Geert  
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    Moroz, V.
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    Choi, M.
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    Cherman, Vladimir  
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    Mercha, Abdelkarim  
    Proceedings paper
    2012, IEEE International 3D System Integration Conference - 3DIC, 31/01/2012, p.9-Apr
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    Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performances

    Mercha, Abdelkarim  
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    Van der Plas, Geert  
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    Moroz, V.
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    De Wolf, Ingrid  
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    Asimakopoulos, Panagiotis
    Proceedings paper
    2010, IEEE International Electron Devices Meeting - IEDM, 6/12/2010, p.26-29
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    Noise coupling between TSVs and active devices: planar nMOSFETs vs. nFinFETs

    Sun, Xiao  
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    Rouhi Najaf Abadi, Alireza
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    Guo, Wei  
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    Bel Ali, K.
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    Rack, M.
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    Roda Neve, Cesar
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    Choi, M.
    Proceedings paper
    2015, IEEE 65th Electronic Components & Technology Conference - ECTC, 26/05/2015, p.260-265
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    Through silicon via to FinFET noise coupling in 3-D integrated circuits

    Rouhi Najaf Abadi, Alireza
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    Guo, Wei  
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    Sun, Xiao  
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    Ben Ali, K.
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    Raskin, J.P
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    Rack, M.
    ;
    Roda Neve, Cesar
    Proceedings paper
    2015, International Conference on IC Design and Technology - ICICDT, 1/06/2015, p.1-4

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