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Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performances
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Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performances
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Date
2010
Proceedings Paper
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APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Mercha, Abdelkarim
;
Van der Plas, Geert
;
Moroz, V.
;
De Wolf, Ingrid
;
Asimakopoulos, Panagiotis
;
Minas, Nikolaos
;
Domae, Shinichi
;
Perry, Dan
;
Choi, M.
;
Redolfi, Augusto
;
Okoro, Chukwudi
;
Yang, Yu
;
Van Olmen, Jan
;
Thangaraju, Sarasvathi
;
Sabuncuoglu Tezcan, Deniz
;
Soussan, Philippe
;
Cho, Jong Hoon
;
Yakovlev, A.
;
Marchal, Pol
;
Travaly, Youssef
;
Beyne, Eric
;
Biesemans, Serge
;
Swinnen, Bart
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1916
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Acq. date: 2025-12-10
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Views
1916
since deposited on 2021-10-18
1
last month
1
last week
Acq. date: 2025-12-10
Citations