Publication:

Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performances

Date

2010
Proceedings Paper
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dc.contributor.authorMercha, Abdelkarim
dc.contributor.authorVan der Plas, Geert
dc.contributor.authorMoroz, V.
dc.contributor.authorDe Wolf, Ingrid
dc.contributor.authorAsimakopoulos, Panagiotis
dc.contributor.authorMinas, Nikolaos
dc.contributor.authorDomae, Shinichi
dc.contributor.authorPerry, Dan
dc.contributor.authorChoi, M.
dc.contributor.authorRedolfi, Augusto
dc.contributor.authorOkoro, Chukwudi
dc.contributor.authorYang, Yu
dc.contributor.authorVan Olmen, Jan
dc.contributor.authorThangaraju, Sarasvathi
dc.contributor.authorSabuncuoglu Tezcan, Deniz
dc.contributor.authorSoussan, Philippe
dc.contributor.authorCho, Jong Hoon
dc.contributor.authorYakovlev, A.
dc.contributor.authorMarchal, Pol
dc.contributor.authorTravaly, Youssef
dc.contributor.imecauthorMercha, Abdelkarim
dc.contributor.imecauthorVan der Plas, Geert
dc.contributor.imecauthorDe Wolf, Ingrid
dc.contributor.imecauthorRedolfi, Augusto
dc.contributor.imecauthorVan Olmen, Jan
dc.contributor.imecauthorSabuncuoglu Tezcan, Deniz
dc.contributor.imecauthorSoussan, Philippe
dc.contributor.imecauthorBeyne, Eric
dc.contributor.imecauthorBiesemans, Serge
dc.contributor.imecauthorSwinnen, Bart
dc.contributor.orcidimecMercha, Abdelkarim::0000-0002-2174-6958
dc.contributor.orcidimecVan der Plas, Geert::0000-0002-4975-6672
dc.contributor.orcidimecDe Wolf, Ingrid::0000-0003-3822-5953
dc.contributor.orcidimecSabuncuoglu Tezcan, Deniz::0000-0002-9237-7862
dc.contributor.orcidimecSoussan, Philippe::0000-0002-1347-6978
dc.contributor.orcidimecBeyne, Eric::0000-0002-3096-050X
dc.date.accessioned2021-10-18T19:04:52Z
dc.date.available2021-10-18T19:04:52Z
dc.date.embargo9999-12-31
dc.date.issued2010
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/17621
dc.source.beginpage26
dc.source.conferenceIEEE International Electron Devices Meeting - IEDM
dc.source.conferencedate6/12/2010
dc.source.conferencelocationSan Francisco, CA USA
dc.source.endpage29
dc.title

Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performances

dc.typeProceedings paper
dspace.entity.typePublication
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