Browsing by Author "Palestri, P."
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Publication Characterization and Advanced Modeling of Dielectric Defects in Low-Thermal Budget RMG MOSFETs Using 1/f Noise Analysis
Journal article2024, IEEE TRANSACTIONS ON ELECTRON DEVICES, (71) 3, p.1745-1751Publication Characterization of DC performance and low-frequency noise of an array of nMOS Forksheets from 300 K to 4 K
Journal article2024, SOLID-STATE ELECTRONICS, (215) May, p.Art. 108881Publication Design of ultra-wideband low-noise amplifiers in 45nm CMOS technology: comparison between planar bulk and SOI FinFET devices
Journal article2009, IEEE Transactions on Circuits and Systems I: Regular Papers, (56) 5, p.920-932Publication Design strategies for SOI FinFET low-noise amplifiers: dealing with flicker noise
Proceedings paper2009, 5th Workshop on the Thematic Network on Silicon Insulator Technology, Devices and Circuits - EUROSOI, 19/01/2009Publication Experimental and physics-based modeling assessment of strain induced mobility enhancement in FinFETs
Publication New insights on the excess 1/f noise at cryogenic temperatures in 28 nm CMOS and Ge MOSFETs for quantum computing applications
Proceedings paper2022, International Electron Devices Meeting (IEDM), DEC 03-07, 2022